View CDP1879CD1X_3301613.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-104 features ? cpu interface for use with general-purpose microprocessors ? time of day/calendar ? reads seconds, minutes, hours ? reads day of month and month ? alarm circuit with seconds, minutes or hours operation ? power down mode ? separate clock output selects 1 of 15 square wave signals ? interrupt output activated by clock output and/or alarm circuit ? date integrity sampling for clock rollover eliminated ? on-board oscillator: - crystal operation cdp1879 at 10v . . . . . . . 4.19mhz, 2.09mhz or 1.048mhz - crystal operation cdp1879c-1 at 5v . . . . . 4.19mhz, 2.09mhz or 1.048mhz or 32khz - external clock operation at 10v or 5v. . . . 4.19mhz, 2.09mhz, 1.048mhz or 32khz ? addressable in memory space or cdp1800 series i/o mode ? low standby (timekeeping) voltage with external clock ? related literature - an7275, guide to the use of cd1879 and cdp1879c1 real time clock pinout cdp1879, cdp1879c-1 (pdip, sbdip) top view description the cdp1879 real-time clock supplies time and calendar information from seconds to months in bcd format. it consists of 5 separately addressable and programmable counters that divide down an oscillator input. the clock input can have any one of 4 possible frequencies, allowing ?exibility in the choice of crystal or external clock sources. using an external 32khz clock source, timekeeping can be performed down to 2.5v (see standby (timekeeping) voltage operation). the device can be memory-mapped for use with any general-purpose microprocessor and has the additional capability of operating in the cdp1800 series input/output mode. the real-time clock functions as a time-of-day/calendar with an alarm capability that can be set for combinations of seconds, minutes or hours. alarm time is con?gured by loading alarm latches that activate an interrupt output through a comparator when the counter and alarm latch values are equal. fifteen selectable square-wave signals are available as a separate clock output signal and can also activate the interrupt output. a status register is available to indicate the interrupt source. the value in an 8 bit control register determines the operational characteristics of the device, by selecting the prescaler divisor and the clock output, and controls the load and alarm functions. a transparent freeze circuit preclude clock rollover during counter and latch access times to assure stable and accurate values in the counters and alarm latches. the cdp1879 is functionally identical to the cdp1879c-1. the cdp1879 has a recommended operating voltage range of 4v to 10.5v, and the cdp1879c-1 has a recommended operating voltage range of 4v to 6.5v. the cdp1879 and the cdp1879c-1 are supplied in 24 lead hermetic dual-in-line side-brazed ceramic packages (d suf?x) and 24 lead dual-in-line plastic packages (e suf?x ). 1 2 3 4 5 6 7 8 9 10 11 12 int reset po wer do wn rd io/ mem tpb/ wr tpa cs a2 a1 a0 v ss 16 17 18 19 20 21 22 23 24 15 14 13 v dd xt al clk db7 db6 db4 db2 db1 db0 xtal db5 db3 out ordering information package temp range 5v 10v pkg. no. pdip -40 o c to +85 o c cdp1879ce1 cdp1879e e24.6 sbdip -40 o c to +85 o c cdp1879cd1 - d24.6 burn-in CDP1879CD1X - d24.6 cdp1879 modes of operation operation function read 1. seconds, minutes, hours, date and month counters 2. status register to identify interrupt source write 1. control register to set device operation 2. seconds, minutes, hours, date and month counters 3. alarm latches for alarm time power down 1. three-state interrupt output with active alarm or clock out circuitry for wake-up control 2. data bus and address inputs are dont care interrupt 1. clock out as source 2. alarm time as source 3. either interrupt can occur during normal or power down mode march 1997 file number 1360.2 cdp1879, cdp1879c-1 cmos real-time clock caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
4-105 absolute maximum ratings thermal information dc supply voltage range, v dd (voltage referenced to v ss terminal) cdp1879 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +11v cdp1879c-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage range, all inputs . . . . . . . . . . . . . . -0.5 to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . 10ma device dissipation per output transistor . . . . . . . . . . . . . . . . 40mw for t a = full package temperature range (all package types) thermal resistance (typical) q ja ( o c/w) q jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 60 n/a sbdip package . . . . . . . . . . . . . . . . . . 50 12 operating temperature range (t a ) package type d, h . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +125 o c package type e . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 o c to +85 o c storage temperature range (t stg ). . . . . . . . . . . .-65 o c to +150 o c lead temperature (during soldering). . . . . . . . . . . . . . . . . . +265 o c at distance 1/16 1/32 in. (1.59 0.79mm) from case for 10s max caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions at t a = fuil package-temperature range, unless otherwise speci?ed. for maximum reliability, operating con- ditions should be selected so that operation is always within the following ranges: parameter limits units cdp1879 cdpl879c-1 min max min max dc operating voltage range 4 10.5 4 6.5 v input voltage range v ss v dd v ss v dd v dc standby (timekeeping) voltage (note 1), v stby t a = -40 o c to +85 o c (note 2) 3 - 3 - v t a = 0 o to +70 o c 2.5 - 2.5 v clock input rise or fall time, t r , t f v dd = 5v - 10 - 10 m s v dd = 10v - 1 - - m s notes: 1. timekeeping function only, no read/write accesses, 32khz external frequency source only, no crystal operation. 2. see standby (timekeeping) voltage operation. cdp1879, cdp1879c-1
4-106 reset am - pm and hour logic prescale oscillator second xtal xt al minute hour day month freeze circuit calendar logic prescale select clock select control register int. status register clock and int. logic clock out int v dd v ss i/o interface second latch minute latch hour latch comparator db0-db7 a0 a1 a2 tpa i-o mem tpb/ wr rd cs po wer do wn address decode and control logic 8-bit data bus figure 1. real-time clock functional diagram table 1. control register bit assignment bit 1, 0 frequency 00 select 01 10 11 32768hz 1.048576mhz 2.097152mhz 4.194304mhz bit 2 start/stop 1 = start 0 = stop bit 3 counter/latch control 0 = write to counter and disable alarm 1 = write to and enable alarm clock select bit 7, 6, 5, 4 0000 - disable m s 0001 - 488.2 m s 0010 - 976.5 m s 0011 - 1953.1 m s 0100 - 3906.2 m s 0101 - 7812.5 m s 0110 - 15.625ms 0111 - 31.25ms 1000 - 62.5ms 1001 - 125ms 1010 - 250ms 1011 - 500ms 1100 - sec. 1101 - min. 1110 - hour 1111 - day table 2. addresses a2 a1 a0 latch, counter seconds 0 1 0 latch, counter minutes 0 1 1 latch, counter hours 1 0 0 counter, day 1 0 1 counter, month 1 1 0 control, register 1 1 1 status register 1 1 1 msb of hours counters (bit 7) is an am-pm bit. 0 = am; 1 = pm bit 6 of hours counter controls 12/24 hr. 1 = 12 hr: 0 = 24 hr. status register: bit 7 msb = alarm interrupt source: bit 6 = clock. msb of month counter (bit 7) is a leap year bit 0 = no, 1 = yes. cdp1879, cdp1879c-1
4-107 static electrical speci?cations at t a -40 o c to +85 o c v dd 5%, unless otherwise speci?ed parameter conditions limits units v o (v) v in (v) v dd (v) cdp1879 cdpl879c-1 min (note 1) typ max min (note 1) typ max ouiescent device current i dd 0, 5 5 - 0.01 50 - 0.02 200 m a 0, 10 10 - 1 200 - - - output low drive (sink) current, data bus and int l ol 0.4 0, 5 5 1.8 4 - - - - ma 0.5 0,10 10 3.6 7 - - - - output high drive (source) current, data bus and int i oh 4.6 0, 5 5 -1.1 -2.3 - -1.1 -2.3 - 9.5 0,10 10 -2.6 -4.4 - - - - output low drive (sink) current, clock out l ol 0.4 0, 5 5 0.6 1.4 - 0.6 1.4 - 0.5 0,10 10 1.2 3 - - - - output high drive (source) current, clock out i oh 4.6 0, 5 5 -1.1 -2.3 - -1.1 -2.3 - 9.5 0,10 10 -2.6 -4.4 - - - - output low drive (sink) current, xt al out l ol 0.4 0, 5 5 0.2 0.9 - 0.2 0.9 - 0.5 0,10 10 0.4 2 - - - - output high drive (source) current, xt al out i oh 4.6 0, 5 5 -0.15 -0.4 - -0.15 -0.4 - 9.5 0,10 10 -0.3 -0.7 - - - - output voltage low-level v ol (note 2) - 0, 5 5 - 0 0.1 - 0 0.1 v - 0,10 10 - 0 0.1 - - - output voltage high level v oh (note 2) - 0, 5 5 4.9 5 - 4.9 5 - - 0, 10 10 9.9 10 - - - - input low voltage v il 0.5, 4.5 0.5, 9.5 - - 5 10 - - - - 1.5 3 - - - - 1.5 - input high voltage v ih 0.5, 4.5 0.5, 9.5 - - 5 10 3.5 7 - - - - 3.5 - - - - - input leakage current i in any input 0, 5 0, 10 5 10 - - - - 1 2 - - - - 1 - m a three-state output leakage current i out 0, 5 0,5 5 - - 1- - 1 0,10 0,10 10 - - 1--- operating current (note 3) external clock 32khz - - 5 - 0.01 0.15 - 0.01 0.15 ma external clock 1mhz - - 5 - 0.2 1 - 0.2 1 external clock 2mhz - - 5 - 0.35 1.5 - 0.35 1.5 external clock 4mhz - - 5 - 0.7 2 - 0.7 2 external clock 32khz - - 10 - 0.03 0.25 - - - external clock 1mhz - - 10 - 0.4 2 - - - external clock 2mhz - - 10 - 0.8 3 - - - external clock 4mhz - - 10 - 1.6 4.5 - - xtal oscillator (note 4) 32khz - - 5 - 0.1 0.25 - 0.1 0.25 xtal oscillator (note 4) 1mhz - - 5 - 0.3 0.5 - 0.3 0.5 xtal oscillator (note 4) 2mhz - - 5 - 0.4 0.6 - 0.4 0.6 xtal oscillator (note 4) 4mhz - - 5 - 0.6 0.8 - 0.6 0.8 xtal oscillator (note 4) 1mhz - - 10 - 1.6 3 - - - xtal oscillator (note 4) 2mhz - - 10 - 1.8 3.5 - - - xtal oscillator (note 4) 4mhz - - 10 - 2 5 - - - cdp1879, cdp1879c-1
4-108 input capacitance c in - - - - 5 7.5 - 5 7.5 pf output capacitance c out - - - - 10 15 - 10 15 maximum clock rise t r , t f and fall times --5- -10- -10 m s --10--1--- notes: 1. typical values are for t a = 25 o c and nominal v dd . 2. i ol = i oh = 1 m a. 3. operating current measured with clockout = 488.2 m s and no load. 4. see table 3 and figure 6 for oscillator circuit information. static electrical speci?cations at t a -40 o c to +85 o c v dd 5%, unless otherwise speci?ed (continued) parameter conditions limits units v o (v) v in (v) v dd (v) cdp1879 cdpl879c-1 min (note 1) typ max min (note 1) typ max programming model write and read registers write only registers bcd format tens 0-5 units 0-9 db7 db0 seconds counter (00-59) tens 0-5 db7 db0 minutes counter (00-59) db7 db0 hours counter (01 - 12 or 00-23) db6 x x tens 0-2 db7 0=am, 1=pm db6 0=24 hr, 1=12 hr tens 0-3 units 0-9 db7 db0 day of month counter (01-28, 29, 30, 31) units 0-9 db7 db0 month counter x tens 0 or 1 (jan=1 dec=12) db7 0=no leap year 1=leap year units 0-9 units 0-9 7 db7 db0 control register 6543210 db0-db1 - frequency select db2 - start/stop db3 - counter/alarm latch control db4-db7 - clock output select db7 db0 seconds alarm latch (00-59) tens 0-5 units 0-9 db7 db0 minutes alarm latch (00-59) tens 0-5 units 0-9 db7 db0 hours alarm latch (01-12 or 00-23 tens 0-2 units 0-9 xx 12 hr, db7=0 am, 1=pm 24 hr, db7=x x db7 db0 read only register x000000 db6 interrupt status register db7=1 alarm circuit activated int. db6=1 clock output activated int. db6 cdp1879, cdp1879c-1
4-109 general operation the real-time clock contains seconds, minutes, and hours, date and month counters that hold time of day/calendar information (see figure 2). the frequency of an intrinsic oscillator is divided down to supply a once-a-second signal to the counter series string. the counters are separately addressable and can be written to or read from. the real-time clock contains seconds, minutes and hour write-only alarm latches that store the alarm time (see fig- ure 3). when the value of the alarm latches and counters are equal, the interrupt output is activated. the interrupt output can also be activated by a clock output transition. the clock output is derived from the prescaler and counters and can be one of 15 square-wave signals. the value in the read- only interrupt status register identi?es the interrupt source. operational control of the real-time clock is determined by the byte in a write-only control register. the 8-bit value in this register determines the correct divisor for the prescaler, a data direction and alarm enable bit, clock output select, and start/stop control (see figure 4). data transfer and addressing are accomplished in two modes of operation, memory mapping and i/o mapping using the cdp1800-series microprocessors. the mode is selected by the level on an input pin. (io/ mem). memory mapping implies use of the address lines as chip selects and address inputs during linear selection or partial or full decod- ing methods. i/o mapping with the cdp1800-series micro- processors involves use of the n line outputs in conjunction with input and output instructions to transfer data to and from memory. register truth table address active signal bit 3 control register register operation a2 a1 ao tpb/ wr rd 0 1 0 x - 0 write seconds counter 0 1 0 - x 0 read seconds counter 0 1 1 x - 0 write minutes counter 0 1 1 - x 0 read minutes counter 1 0 0 x - 0 write hours counter 1 0 0 - x 0 read hours counter 1 0 1 x - 0 write date counter 1 0 1 - x 0 read date counter 1 1 0 x - 0 write month counter 1 1 0 - x 0 read month counter 0 1 0 x - 1 write seconds alarm latch 0 1 1 x - 1 write minutes alarm latch 1 0 0 x - 1 write hours alarm latch 1 1 1 x - - write control register 1 1 1 - x - read int. status register cdp1879, cdp1879c-1
4-110 reset am - pm and hour logic prescale oscillator second xtal xt al minute hour day month freeze circuit calendar logic prescale select clock select control register int. status register clock and int. logic clock out int v dd v ss i/o interface second latch minute latch hour latch comparator db0-db7 a0 a1 a2 tpa io/ mem tpb/ wr rd cs po wer do wn address decode and control logic 8-bit data bus figure 2. functional diagram - time counters highlighted cdp1879, cdp1879c-1
4-111 operational sequence power is applied and the real-time clock is reset. this sets the interrupt output pin high. after the cs pin is set high and with address 7 on the address input lines, the control register is loaded via the data bus to con?gure the clock. with selective addressing, the seconds through month counters are then written to and loaded to set the current time. the real-time clock will now hold the current wall clock time, with an accuracy determined by the crystal or external clock used. if the alarm function is desired, the control register is accessed and loaded again. this new byte will allow subse- quent time data to be entered into the seconds, minutes and hours alarm latches. this sequence is also used when select- ing one of the 15 available clock-out signals. if the alarm function was selected, the interrupt output pin will be set low when the values in the seconds, minutes and hour alarm latches match those in the seconds, minutes and hour counters. if one of the 15 sub second-to-day clock outputs is selected by the byte in the control register, the clock output pin tog- gles at that frequency (50% duty cycle) the interrupt output will also be set low on the ?rst clock out negative transition. the interrupt source (alarm or clock out) can be determined by reading the interrupt status register. the clock output can be deselected by placing zero in the upper nibble of the con- trol register if the alarm function is selected as the only inter- rupt source. counters the counter section consists of an on-board oscillator, a prescaler and 5 counters that hold the time of day/calendar information (see figure 2). 1 of 4 possible external crystals determine the frequency of the on-board oscillator (32,768hz, 1.048576mhz, 2.097152mhz, 4.194304mhz). the oscillator output is divided down by a pres- reset am - pm and hour logic prescale oscillator second xtal xt al minute hour day month freeze circuit calendar logic prescale select clock select control register int. status register clock and int. logic clock out int v dd v ss i/o interface second latch minute latch hour latch comparator db0-db7 a0 a1 a2 tpa io/ mem tpb/ wr rd cs po wer do wn address decode and control logic 8-bit data bus figure 3. functional diagram - alarm circuit, clock output, interrupt, and status registers highlighted cdp1879, cdp1879c-1
4-112 caler that supplies a once-a-second pulse to the counters. the seconds counter divide the pulse by 60 and its output clocks the minute counter every 60 seconds further division by the minutes, hours, day of month and month counters result in 5 counters holding data that re?ect the time/calendar from sec- onds to months. the counters are addressed separately and bcd data is transferred to and from via the data bus. the most signi?cant bit of the hours counter (bit 7) is user programmed to indicate am or pm and will be inverted every 12th hour. (0=am, 1=pm). bit 6 of the hours counter is user programmed to enable the hours counter for 12 or 24 hour operation. (0=24,1=12). if 24-hour operation is selected, the am-pm bit is don't care, but still toggles every 12th hour. writing to the sec- onds counter resets the last 7 stages of the prescaler, allowing time accuracy to approximately 1/100 of a second. the most signi?cant bit of the month counter is a leap year bit. if it is set to 1, the counter will count to february 29, then roll to march 1. if set to 0 it will go to march 1st after february 28th. alarm and interrupt status register the alarm circuit consists of 1) seconds, minutes and hour alarm latches that hold the alarm time, 2) the outputs of the seconds, minutes and hour counters, and 3) a comparator that drives an interrupt output. the comparator senses the counter and alarm latch values and activates the interrupt output (active low) when they are equal (see figure 3). the write-only alarm latches have the same addresses as their comparable counters. bit 3 in the control register deter- mines data direction to the latches or counters and alarm enabling. for example, during a write cycle, if bit-3 in the control register is a 1, addressing the seconds counter or alarm latch will load the seconds alarm latch from the data bus and will enable the alarm function. conversely, if bit-3 in the control register is a 0, addressing the seconds counter or alarm latch during a write cycle will place the value on the data bus into the seconds counter and will disable the alarm function. the interrupt output can be activated by the alarm circuit or the clock output. when an interrupt occurs, the reset am - pm and hour logic prescale oscillator second xtal xt al minute hour day month freeze circuit calendar logic prescale select clock select control register int. status register clock and int. logic clock out int v dd v ss i/o interface second latch minute latch hour latch comparator db0-db7 a0 a1 a2 tpa io/ mem tpb/ wr rd cs po wer do wn address decode and control logic 8-bit data bus figure 4. functional diagram - control register highlighted cdp1879, cdp1879c-1
4-113 upper two bits of the interrupt status register identify the interrupt source. the interrupt status register has the same address as the control register. addressing the interrupt sta- tus register with the rd line active will place these register bits on the data bus. bits 0-5 are held low. a 1 in bit-6 rep- resents a clock output transition as the interrupt source. a 1 in bit-7 will identify the alarm circuit as the interrupt source. activating the reset pin (active low) resets the hour latch to 30 which prevents a match between alarm and time regis- ters during an initialization procedure. activating the reset pin or writing to the control register resets the interrupt out- put (high) and clears the interrupt status register clock output one of 15 counter and prescaler over?ows can be selected as a 50% duty cycle output signal that is available at the clock out pin. the frequency is selected by the upper nibble in the control register. for example, selecting a one-second clock output will result in a repetitive signal that will be high for 500ms and low for the same period. the high-to-low tran- sition of the output signal will set the clock bit in the status register and activate the interrupt output. the level of the clock out signal is derived from the value in the counter. example - if hours clock is selected and the minutes counter holds 4 minutes, the clock out will be low for 26 minutes and high for 30 minutes thereafter, the clock out will toggle at a 50% duty cycle rate (see table 1 and figure 3). the 8-bit value in the control register determines the follow- ing: 1. bit 0 and 1 - frequency select - since there are one of 4 possible crystals the oscillator in the real-time clock can operate with, these bit levels determine the prescaler divi- sor so that an accurate one second pulse is supplied to the counter series string. 2. bit 2 - start-stop control - counter enabling is controlled by the value at this location. a 1 will allow the counters to function and a 0 in this location will disable the counters. 3 bit 3 - counter/latch control - the level at this location controls two functions. it is required since the counters and alarm latches have the same addresses. 1) a 0 in bit-3 will direct subsequent data to or from the counter selected and the alarm function will be disabled. 2) a 1 in bit-3 will direct subsequent data to or from the alarm latch and will enable the alarm. 4. bits 4 to 7 - clock select - these bits select one of 15 square-wave signals that will be present at the clock- out pin. if bit-4 to bit-7 are zero's, the clock output pin will be high. if a clock is selected, the ?rst high-to-low clock out transition will activate the interrupt pin (active low) and place a 1 in bit-6 of the status register. writing to the control register or activating the reset pin will set the inter- rupt pin high and reset the interrupt status register. normal operation requires the control register to be written to and loaded ?rst with a control word. however, subsequent writing to a counter if a clock out is selected may cause an interrupt out signal. therefore, clock-out should be dese- lected by writing zero's into bit-4 through bit-7 if the interrupt is used. when the counters are loaded, the control register is again written to with the value in the upper nibble selecting the clock out signal. see table 1. read and write signals when the io/ mem pin is low, the real-time clock is enabled for memory mapped operation. data on the bus is placed in, or read from a counter, alarm latch or register by 1) placing the cs pin high, 2) selective addressing, 3) placing the tpb/ wr pin low during a write cycle with the rd pin high or 4) setting the rd pin low during a read cycle with this tpb/ wr pin high. the i/o mapping mode used with the cdp1800 series microprocessor is selected by setting the io/ mem pin high. the tpb/ wr pin on the real-time clock is connected to the tpb output pin of the microprocessor. data on that bus is written to or read from the counters, latches and registers by 1) placing the cs pin high, 2) selective addressing utilizing the microprocessor n lines and i/o instructions, 3) placing the tpb/ wr pin high with the rd pin low during an output or write operation (data is latched on tpb's trailing edge), 4) setting the rd line high during an input or read operation. data is placed on the bus by the real-time clock between the trailing edges of tpa and tpb. freeze circuit since writing to or reading from the counters or alarm latches is performed asynchronously, the once-a-second signal from the prescaler may pulse the counter series string during these operations. this can result in erroneous data. to avoid this occurring, a transparent freeze circuit' is incor- porated into the real-time clock. this circuit is designed to trap and hold the one-second input clock transition if it occurs during access times. when the operations are com- pleted, it is inserted into the counter series string. to utilize the freeze circuit, address 1 (a0 = 1, a1 = 0, a2 = 0) is selected ?rst while performing a write operation. read or write accesses may now be performed with assurance the data is stable. all operations must be concluded within bit 1 bit 0 frequency 0 0 32,768hz 0 1 1.048576mhz 1 0 2.097152mhz 1 1 4.194304mhz 7 bit 6543210 control register byte bit control register (see table 1 and figure 4) cdp1879, cdp1879c-1
4-114 250ms of the address 1 access. in memory mapping any dummy write operation after selecting address 1 will set the freeze circuit. if using the i/o mode, a 61 output instruction will perform the same function. there is no time restriction on subsequent accesses as long as the read or write opera- tions are preceded by selecting address 1. power down power down operation is initiated with a low signal on the "power down input pin. in conjunction with the interrupt output, it is used to supply external control circuits with a 3 level control signal. the operating current is not appreciably reduced during power down operation. when power down is initiated, any inputs on the address or data bus are ignored. the clock output is set low. the interrupt output is three-stated. if enabled previously, the alarm circuitry is active and will set the interrupt output pin low when alarm time occurs. the interrupt output will also go low if a clock was selected and an internal high-to-low transition occurs during power down. the clock output pin will remain low. if power down is initiated in the middle of a read or write sequence, it will not become activated until the read or write cycle is completed. pin functions v dd , v ss - power and ground for device. db0 - db7 - data bus - 8-bit bidirectional bus that trans- fers bcd data to and from the counters, latches and regis- ters. a0, a1, a2 - address inputs that select a counter, latch or register to read from or write to. tpa - strobe input used to latch the value on the chip select pin. cs is latched on the trailing edge of tpa. during mem- ory mapping, it is used to latch the high order address bit used for the chip select. when the real-time clock is used with other microprocessors, or when the high order address of the cdp1800 series microprocessor is externally latched, it is connected to v dd . in the input/output mode, it is used to gate the n lines. io/mem - tied low during memory mapping and high when the input/output mode of the cdp1800 series microproces- sor is used. rd, tpb/wr - direction signals - active signals that deter- mine data direction ?ow. in the memory mapped mode, data is placed on the bus from the counters or status register when rd pin is active. data is transferred to a counter, latch or the control register when rd is high and tpb/ wr is active and latched on the trailing edge (low to high) of the tpb/ wr signal. in the input/output mode, data is placed on the bus from a counter or status register when rd is not active between the trailing edges of tpa and tpb. data on the bus is written to a counter, latch, or the control register during tpb when rd is active and latched on tpb's trailing edge. the following con- nections are required between the microprocessor and real- time clock in the cdp1800 series i/o mode. microprocessor real-time clock cs - chip select - used to enable or disable the inputs and outputs. tpa is used to strobe and latch a positive level on this pin to enable the device. xtal and xtal - the frequency of the internal oscillator is determined by the value of the crystal connected to these pins. xtal may be driven directly by an external frequency source. clock out - 1 of 15 square wave frequencies will appear at this pin when selected. during power down, this pin will be placed low, and will be high during normal operation when the clock is deselected. power down - power down control - a low on this pin will place the device in the power down mode. int - interrupt output - a low on this pin indicates an active alarm time or high-to-low transition of the clock out signal. reset - a low on this pin clears the status register and places the interrupt output pin high. frequency input requirements the real-time clock operates with the following frequency input sources: 1. an external crystal that is used with the on-board oscilla- tor. the oscillator is biased by a large feedback resistor and oscillates at the crystal frequency (see figure 6, table 3). 2. an external frequency input that is supplied at the xtal input. xt al is left open (see figure 5). a typical external oscillator circuit is shown in figure 7 in section, standby (timekeeping) voltage operation. mrd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . rd tpb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tpb/ wr tpa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tpa n lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address lines io/ mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd cdp1879, cdp1879c-1
4-115 design considerations for stable crystal oscillation 1. stray capacitances should be minimized for best oscilla- tor performance. circuit board traces should be kept to a maximum of 1 inch, and there should be no parallel traces. 2. a signal line or power source line must not cross or go near the oscillator circuit line. 3. it is advisable to put a 0.1 m f capacitor between v dd and v ss of the cdp1879. standby (timekeeping) voltage operation when any one of the four speci?ed crystals is used with the on-board oscillator, the real-time clock can operate at a minimum of 4v v dd . however, at 32khz the clock will run (timekeeping only, no device read/write accesses) down to 3v at -40 o c to +85 o c and 2.5v at 0 o to +70 o c. to achieve this low voltage operation, an external 32khz clock source must be supplied at the xtal input (see figure 7). the standby requirements for chip select/deselect are listed in table 4, and figure 8 indicates the timing waveforms. figure 9 illustrates the typical timekeeping curve over the full temperature range. table 3. typical oscillator circuit parameters for suggested oscillator circuit, see figure 6 parameter 4.197mhz 2.097mhz 1.049mhz 32768hz (note) units r f 22 22 22 22 m w c 0 39 39 39 39 pf c 1 5555pf r s - - - 200 k w c l - - - 91 pf crystal impedance 73 200 200 50k (max.) w note: cdp1879c-1 only. figure 5. connections for an external frequency source applied to real-time clock cdp1879 pin 23 xt al external frequency source pin 22 xtal figure 6. suggested oscillator circuit applied to real-time clock (see table 3) cdp1879 pin 23 xt al pin 22 parallel resonant crystal xt al r s c l c o c i r f 5 p f 200k r l 39 p f 22 meg. r f 1 2 3 14 4 +3v 24 23 22 1/3 cd54/74hc04 cdp1879 figure 7. typical external clock-source circuit cdp1879, cdp1879c-1
4-116 applications a typical application for this real-time clock is as a wake-up control to a cpu to reduce total system power in intermit- tent-use systems. a hookup diagram illustrating this feature is shown in figure 10. in this con?guration, the alarm and power-down features of the cdp1879 are utilized in the con- trol of the sleep and wake-up states of the cpu. a typical shut-down/start-up sequence for this system could proceed as follows: 1. the cpu has ?nished a current task and will be inactive for the next six hours. 2. the cpu loads the cdp1879 alarm registers with the desired wake-up time. 3. the cdp1800 q output is set high, which stops the cpu oscillator (as an alternative, in an nmos system, power to all components except the clock chip could be shut off). 4. this q output signal is received by the cdp1879 as a power-down signal. 5. the cdp1879 three-states the interrupt output pin. 6. the cdp1879 eventually times out, and sets an alarm by driving the int output low. 7. the alarm signal resets the cpu (to avoid oscillator start- up problems) and ?ags the processor for a warm-start routine. 8. the cpu, once into its normal software sequence, writes to the cdp1879 control register to reset the interrupt request. standby (timekeeping) characteristics at full temperature range parameter v dd (v) v stby (v) limits units cdp1879 cdp1879c-1 min max min max chip deselect to standby t cstby (timekeeping) voltage time 5 10 2.5, 3 2.5, 3 2 1 - - 2 - - - m s recovery to normal t rc operation time 5 10 2.5, 3 2.5, 3 2 1 - - 2 - - - note: 1. t r , t f 3 1 m s figure 8. standby (timekeeping) voltage and timing waveforms figure 9. typical standby (timekeeping) voltage vs full temperature range 0.95 v dd standby voltage mode v stby 0.95 v dd t stby v ih v il t r (note 1) t f (note 1) t rc v ih v il v dd cs 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 external clock source of 32khz typical standby (timekeeping) voltage standby (timekeeping voltage (v) (v stby + v dd ) full temperature range - o c 3v (-40 o c t +85 o c) 2.5v (-0 o c t +70 o c cdp1879, cdp1879c-1
4-117 figure 10. cpu wake-up circuit using the cdp1879 real-time clock figure 11. typical cdp1802 memory mapped system xt al xtal a0 a1 a2 io/ mem cdp1879 pd int v dd v dd 1/2 cd40107 1/2 cd40107 v dd n0 n1 n2 xt al cdp1800 q clear xt al efi v dd clear mwr mrd tpa interr upt ma0 ma1 ma2 cdp1802 memory cdp1879 db0 - db7 data bus address lines reset tpb/ wr rd tpa interr upt a0 a1 a2 io/ mem xtal xt al clock out cs v ss ma7 cdp1879, cdp1879c-1
4-118 figure 12. cdp1800 series memory mapped write cycle timing waveforms figure 13. cdp1800 series memory mapped read cycle timing waveforms figure 14. typical cdp1802 input/output mapped system latch high-order address for cs high byte low byte data latched valid data data from cpu tpb/ wr address tpa to real time clock high byte low byte valid data output drivers enabled disabled data from rd address tpa real time clock to cpu clear tp a mrd tpb interr upt n0 n1 n2 cdp1802 memory cdp1879 db0 - db7 address lines reset tpa rd tpb/ wr interr upt a0 a1 a2 io/ mem xtal xt al clock out v dd cs cdp1879, cdp1879c-1
4-119 figure 15. cdp1800 series input/output mapping timing waveforms with output instruction figure 16. cdp1800 series input/output mapping timing waveforms with input instruction dynamic electrical speci?cations at t a -40 o c to +85 o c , input t r , t f = 10ns, c l = 50pf parameter v dd (v) limits units cdp1879 cdp1879c-1 (note 1) min max (note 1) min max read cycle times (see figure 17) data access from address t da 5 - 400 - 400 ns 10 - 190 - - read pulse width t rd 5 270 - 270 - 10 160 - - - data access from read t dr 5 - 375 - 375 10 - 170 - - address hold after read t rh 50 - 0 - 10 0 - - - output hold after read t dh 5 50 230 50 230 10 40 130 - - chip select setup to tpa t cs 5 50 - 50 - 10 30 - - - note: 1. time required by a limit device to allow for the indicated function. valid data data from memory n lines rd tpa to real-time clock tpb/ wr data latched valid data output drivers enabled output drivers disabled data from rd tpb/ wr tpa real-time clock to memory n lines cdp1879, cdp1879c-1
4-120 figure 17. read cycle timing waveforms address/chip select read tpa data to cpu t cs t rh t rd t dr t da t dh dynamic electrical speci?cations at t a -40 o c to +85 o c, input t r , t f = 10ns, c l = 50 pf parameter v dd (v) limits units cdp1879 cdp1879c-1 (note 1) min max (note 1) min max write cycle times (see figure 18) address setup to wr ite t as 5 10 225 110 - - 225 - - - ns wr ite pulse width t wr 5 10 150 70 - - 150 - - - data setup to wr ite t ds 5 10 65 30 - - 65 - - - address hold after wr ite t ah 5 10 0 0 - - 0 - - - data hold after wr ite t wh 5 10 150 80 - - 150 - - - chip select setup to tpa t cs 5 10 50 30 - - 50 - - - note: 1. time required by a limit device to allow for the indicated function. cdp1879, cdp1879c-1
4-121 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 figure 18. write cycle timing waveform address/chip select write tpa data to real-time clock t cs t ah t as t ds t wr t wh cdp1879, cdp1879c-1

▲Up To Search▲

Price & Availability of CDP1879CD1X

	To Download CDP1879CD1X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .